1. Field of the Invention
The present invention relates to an FM receiver for receiving FSK binary signals and more particularly to a signal processing circuit such as a data limiter with a capacitively coupled voltage clamped input for exhibiting fast response time in the presence of input disturbances.
2. Background of the Invention
A block diagram of a prior art FM receiver system suitable for use in a synchronous paging system is illustrated in FIG. 1. The receiver comprises the antenna 10 which receives an RF signal and transmits it to a receiver 12 where the RF signal is amplified and converted into a first intermediate frequency (IF) signal by an RF amplifier and first mixer, respectively. This IF signal is preferrably directed to the receiver's back end where the first IF signal is converted to a second IF signal (in a dual conversion receiver) amplified, limited, filtered and demodulated. The voltage level of the output signal at output 14 represents the coded binary data. Output 14 may of course be viewed as having a Thevenin equivalent of a voltage source in series with an output resistance which is not shown. The output 14 of the receiver 12 is capacitively coupled to the input 15 of a data limiter 16 via a coupling capacitor 18. Internal or external limiter bias resistors (not shown) are normally used to bias the data limiter 16. The output of the data limiter 16 is directed to a data processor 20 for further desired processing.
The FM receiver system also includes one or more switches 22 (normally transistors) connected between the various components of the FM receiver system and the power supply. This switch is periodically turned ON and OFF by battery saver circuit 24 to provide a battery saving feature, which is a technique well known to those skilled in the art. A switch 26 (also, normally a transistor) is periodically closed to precharge the coupling capacitor 18, preferrably by placing a resistor 27 in parallel with the limiter bias resistors and input impedance thereby reducing the overall RC time constant. Switch 26 is normally closed simultaneously with the switch 22 but normally remains closed for a shorter time than switch 22 to provide this precharging feature.
Normally, in situations where it is necessary to pass digital data from the receiver 12 to the data limiter 16, capacitor 18 will be a relatively large value in order to pass the low frequency information in digital signals. Thus, a long time may be required to charge the capacitor 18, especially when it is connected to a high impedance such as the limiter bias resistors for the data limiter 16. A long charge time necessitates that receiver "ON" time be increased correspondingly to ensure that capacitor 18 is charged to its correct bias point and that valid data is delivered to the data processor 20 during the data decoding interval. The battery saver feature is clearly degraded by the extended receiver "ON" time since this consumes more battery energy than is desirable. The switch 26 is used to alleviate this situation by providing a momentary low impedance charge path in parallel with the data limiter's bias resistors immediately upon receipt of power from the battery saver 24, that is, when the switch 22 is closed. This allows capacitor 18 to more rapidly charge to a voltage dependent upon the average value of the incoming data. If the incoming data can be depended upon to have no long strings of ones or zeros the charging of capacitor 18 will closely approximate the desired bias voltage. Data decoding of the received bit stream can begin more rapidly and continue until the battery voltage B+ is again removed by switch 22, thereby enhancing the battery saver feature.
However, one problem still exists even when the coupling capacitor 18 is precharged. Under ideal conditions (an alternating one-zero data pattern) the average voltage level at the output of the receiver 12 will be at the desired carrier reference voltage, that is the voltage level which corresponds to an undeviated RF carrier signal. During the precharge interval, capacitor 18 will charge to a bias voltage which is consistent with this carrier reference voltage and proper data decoding will occur. If a long string of ones or zeros is received immediately before the opening of switch 26 the average DC voltage at the receiver output 14 will be offset from the desired reference. The average DC voltage is increased if a large number of ones are received or decreased if a large number of zeros are received.
Thus, relatively substantial DC voltage offsets from the correct bias voltage across capacitor 18 may still occur if this technique is used in an asynchronous system with unpredictable data patterns. This may result in erroneous outputs from the data limiter 16, long response time (the delay required between receipt of a signal and occurrence of valid data at the limiter output), and may ultimately result in the end user receiving no message or an erroneous message which differs from the originally transmitted message.